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[Other] xapp858[1]

Description: XAPP858 - 利用 Virtex-5 FPGA 实现的高性能 DDR2 SDRAM 接口数据采集 本应用指南描述了用于实现 667 Mbps（333 MHz）高性能 DDR2 SDRAM 接口的控制器和数据采集的技巧。 本数据采集技巧使用了输入串行器/解串器（ISERDES）和输出串行器/解串器（OSERDES）的功能。-XAPP858-use Virtex-5 FPGA high-performance DDR2 SDRA M Interface Data Acquisition Guide describes the application for achieving 667 Mbps (333 MHz) high-performance DDR 2 SDRAM Interface controller and data acquisition techniques. The data collection techniques used serial input/Solution Series (ISERDES) and serial output/Solution Series (O Legacy) function.
Platform: | Size: 296960 | Author: mingming | Hits:

[Compress-Decompress algrithms] DDR2_sdram

Description: DDR2 的控制器，它是由LATTICE的编译器生成。-DDR2 controller, it is by the compiler-generated LATTICE.
Platform: | Size: 966656 | Author: 李国 | Hits:

[Software Engineering] DDR

Description: 关于DDR SDRAM的详细原理和时序分析,对于开发设计有很大使用价值-DDR SDRAM on detailed principles and timing analysis, design for the development of a great value
Platform: | Size: 2201600 | Author: 王平 | Hits:

[VHDL-FPGA-Verilog] ddr2sdram_spartan3s700an.tar

Description: It is a first time code being developed to designers who want to get your DDR2 SDRAM on-board in Spartan 3AN Starter Kit - Diligent fully working.-It is a first time code being developed to designers who want to get your DDR2 SDRAM on-board in Spartan 3AN Starter Kit- Diligent fully working.
Platform: | Size: 1488896 | Author: under | Hits:

[VHDL-FPGA-Verilog] modelsim_ddr2sdram_spartan3s700an.tar

Description: Modelsim DDR2 SDRAM files
Platform: | Size: 280576 | Author: under | Hits:

[VHDL-FPGA-Verilog] Micron_SDRAM_DDR2Simulation_model_Verilog

Description: DDR2 SDRAM仿真模型，适合于ModelSim下工作，请先阅读readme-DDR2 SDRAM Simulation Model which is suitable for modelsim. Please read readme file firstly.
Platform: | Size: 20480 | Author: rar | Hits:

[VHDL-FPGA-Verilog] 1189152740

Description: DDR2 SDRAM 控制器的FPGA实现-DDR2 SDRAM controller FPGA to achieve
Platform: | Size: 84992 | Author: 白皓 | Hits:

[Other] Micron_DDR

Description: DDR2 SDRAM 颗粒初始化以及读写操作时序-Particles as well as the DDR2 SDRAM initialization timing to read and write operations
Platform: | Size: 432128 | Author: robert.wang | Hits:

[OS Develop] ddr2_device_operation_timing_diagram_may_07_1

Description: DDR2时序规范，DDR· DDR2时序规范，DDR·-DDR2 timing norms, DDR DDR2 timing norms, DDR
Platform: | Size: 1933312 | Author: yangjian | Hits:

[VHDL-FPGA-Verilog] Xil3SD1800A_MIG_simplifiedUI_vlog_v92

Description: verilog 实现的spartan 3A dsp start kit DDR2 SDRAM 控制器-verilog achieved spartan 3A dsp start kit DDR2 SDRAM controller
Platform: | Size: 908288 | Author: ma yirong | Hits:

[Documents] ddr2_sdram_controller

Description: 关于DDR2 SDRAM 控制器的相关论文资料-ddr2_sdram_controller
Platform: | Size: 5675008 | Author: 王颖伟 | Hits:

[VHDL-FPGA-Verilog] c_xapp260

Description: xilinx应用指南xapp260的中文翻译版本。利用 Xilinx FPGA 和存储器接口生成器简化存储器接口。本白皮书讨论各种存储器接口控制器设计所面临的挑战和 Xilinx 的解决方案，同时也说明如何使用 Xilinx软件工具和经过硬件验证的参考设计来为您自己的应用（从低成本的 DDR SDRAM 应用到像 667 Mb/sDDR2 SDRAM 这样的更高性能接口）设计完整的存储器接口解决方案。-The use of Xilinx FPGA and Memory Interface Generator to simplify memory interface. This white paper discusses the various memory interface controller design challenges facing Warfare and Xilinx solutions, but also explains how to use Xilinx Software tools and hardware-proven reference designs to be for your own With (from low-cost DDR SDRAM applications to such as 667 Mb/s This higher performance DDR2 SDRAM interface) design a complete deposit Storage device interface solution.
Platform: | Size: 1123328 | Author: 陈阳 | Hits:

[VHDL-FPGA-Verilog] c_xapp454

Description: 这是xilinx应用指南xapp454的中文版本。本应用指南说明与 Micron DDR2 SDRAM 器件连接时，Spartan™ -3 器件中 DDR2 SDRAM 存储器接口的实现。本文档先简单介绍了 DDR2 SDRAM 器件的特性，然后对 DDR2 SDRAM 存储器接口的实现进行了详细说明。-This is the xilinx application note xapp454 the Chinese version. This application note and the Micron DDR2 SDRAM device is connected, Spartan ™ -3 devices DDR2 SDRAM memory interface implementation. This document briefly describes the DDR2 SDRAM device features, and then the realization of DDR2 SDRAM memory interface is described in detail.
Platform: | Size: 217088 | Author: 陈阳 | Hits:

[VHDL-FPGA-Verilog] c_xapp858

Description: 这是xilinx应用指南xapp858的中文版本。本应用指南介绍了用于实现高性能 DDR2 SDRAM 接口的控制器和数据采集技术。本数据采集技术使用了每一个 Virtex™ -5 I/O 都具有的输入串行器/ 解串器 (ISERDES) 和输出双倍数据速率 (ODDR) 的功能。-This is the xilinx application note xapp858 the Chinese version. This application note describes the interface used to achieve high-performance DDR2 SDRAM controller and data acquisition technology. This data collection technique used in each Virtex ™ -5 I/O has an input serializer/deserializer (ISERDES) and output double data rate (ODDR) function.
Platform: | Size: 447488 | Author: 陈阳 | Hits:

[VHDL-FPGA-Verilog] AMBA

Description: 基于AMBA总线的DDR2 SDRAM控制器研究与实现-AMBA bus-based Research and Implementation of DDR2 SDRAM Controller
Platform: | Size: 209920 | Author: guoxiaojin | Hits:

[Other] ddr_ddr2_sdram9.0

Description: altera 公司提供的ddr_ddr2_sdram9.0，DDR2 SDRAM 源代码-altera provided ddr_ddr2_sdram9.0, DDR2 SDRAM source code
Platform: | Size: 912384 | Author: tiantian | Hits:

[VHDL-FPGA-Verilog] Virtex-5-FPGA_DDR2_SDRAM_data

Description: Virtex-5 FPGA实现的高性能 DDR2 SDRAM数据采集，需要对V5有一定基础的人学习-Virtex-5 FPGA DDR2 SDRAM to achieve high-performance data acquisition, the need for V5 have to learn some basic
Platform: | Size: 436224 | Author: apple_rao | Hits:

[VHDL-FPGA-Verilog] Spartan3-FPGA--DDR2-SDRAM

Description: FPGA学习资料，入门级掌握资料，ddr2内存-Spartan-3 FPGA 的 DDR2 SDRAM
Platform: | Size: 218112 | Author: liu | Hits:

[Software Engineering] byNeyno_

Description: micron data sheet for designing the ddr2 sdram controller part1
Platform: | Size: 16384 | Author: ravi kishore | Hits:

[Technology Management] Design-of-DDR2-SDRAM-Interface

Description: 高速图像处理系统中DDR2-SDRAM接口的设计-Design of DDR2-SDRAM Interface in High-speed Image Processing System
Platform: | Size: 467968 | Author: dongfaxiang | Hits:
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